Due to its superior conductive and non-corrosive characteristics, gold is a “material of choice” for making electrical connections between electronic components. For example, it is well known to make a plurality of wire bond connections between conductive pads on a semiconductor die and inner ends of leadframe fingers. This is cited as one example of making permanent connections between a first, “active” electronic component (the die) and a second “passive” electronic component (the leadframe).
The present invention advantageously employs wire-bonding equipment in which, generally, wire (e.g., gold wire) is supplied from a spool through a capillary (also referred to as a “bonding head”) and is bonded to a substrate. Generally, the nature of the bonding head will be determined by the nature of the bond to be made thereby. When the bonding head is for making a ball bond, it will generally be a “capillary”. When the bonding head is for making a wedge bond, it will generally be a “wedge”, these terms having recognized meanings in the art. To simplify matters, in the main hereinafter, the term “capillary” will be employed to indicate a bonding head suitable for making either ball or wedge bonds, applying thermal energy and/or compression during bonding.
The following U.S. patents (cited, when applicable, by patent number, first named inventor, month/year of issue, and US Class/Subclass), incorporated by reference herein, are indicative of the state of the art of wirebonding:
(a) U.S. Pat. No. 5,110,032 (Akiyama, et al.; 5/92; USCL 228/102). entitled METHOD AND APPARATUS FOR WIRE BONDING, discloses wire (13) supplied from a wire spool (12) through a capillary (10). (In this patent, the wire 13 is insulated.) A control unit (20) is shown which includes a CPU (processor) and a memory unit (storage for software commands). The control unit exercises control over movement of the capillary, and over a discharge power circuit (18) which, in conjunction with a discharging electrode (17) is used to sever the wire with a discharge voltage.
(b) U.S. Pat. No. 3,460,238 (Christy, et al.; 8/69; USCL 227/111), entitled WIRE SEVERING IN WIRE BONDING MACHINES, is directed to a technique whereby the wire severing operation in a wirebonder comprises moving the bonding needle (or “capillary”, as used herein) with holding pressure sufficient to frictionally engage the wire and insufficient to deform the wire away from the bond area. This patent is cited as exemplary of the fact that wire-bonding has been known for decades, and also of the fact that it is generally undesirable to “deform” the wire while moving the capillary.
(c) U.S. Pat. No. 5,095,187 (Gliga; 3/92; USCL 219/68), entitled WEAKENING WIRE SUPPLIED THROUGH A WIRE BONDER, discloses wire-bonding techniques wherein a wire is bonded to a contact on an electronic component by the application of one or a combination of heat, pressure and vibration. This patent discusses weakening or severing the wire by localized application of heat, and how the severing operation may result in a broadened portion on the severed end of the wire. The severing heat may be applied to the wire by means of an electrode from which an electric field can be made to extend to the wire such that an arc is created between the electrode and the wire. This patent describes a severing technique wherein a first portion of the arc is of a first polarity for weakening of the wire, and a second portion of the arc is of a reverse polarity for controlling dispersion of charged particles emitted from the wire.
(d) U.S. Pat. No. 4,860,433 (Miura; 8/89; USCL 29/605), entitled METHOD OF MANUFACTURING AN INDUCTANCE ELEMENT, discloses a technique of winding a coil of fine copper wire on a spool member on a substrate. The copper wire is insulated. It is known that the insulation will be removed from the end of the wire when an electronic flame off (EFO) spark severs the wire, such as at the conclusion of making a previous bond. An end portion of the wire is bonded to a conductive path on the substrate. Then, either the capillary or the substrate is rotated, and a table supporting the substrate may be moved in the vertical direction, to wind the coil of fine copper wire on the spool member. Finally, an opposite end portion of the wire is bonded to another conductive path on the substrate.
Packaging is another milieu (field of endeavor) wherein it is important to effect a plurality of electrical connections between a first electronic component and a second electronic component. For example, in a ceramic package, a semiconductor die is disposed in a cavity in a ceramic package and (typically) wire-bonded to conductive traces extending into the cavity. A plurality (e.g., an array) of pins are disposed on an external surface of the package, and the pins connected by internal traces (patterned conductive layers) and vias to the conductive traces extending into the cavity. The package may then be mounted to a printed circuit board (PCB) having a corresponding plurality (e.g., array) of holes, each hole receiving a corresponding one of the package pins. The pins are typically soldered to the plated-through holes in the PCB to effect a permanent connection between the first electronic component (the packaged semiconductor device) and the second electronic component (the PCB). Alternatively, the package may be received by a socket having a corresponding plurality (e.g., array) of holes, each hole receiving one of the package pins, to effect a temporary connection between the first electronic component (packaged semiconductor device) and the second electronic component (socket).
It is generally well known to protect semiconductor devices against moisture. To this end, various packages exhibit various degrees of hermeticity—ceramic packages generally providing superior protection against the environment at relatively high cost, plastic (e.g., resin) and PCB-type (encapsulated) packages exhibiting relatively poor protection against the environment at relatively low cost, to name a few. In order to have the “the best of both worlds”—namely good hermeticity at low cost, it is known to coat bond wires and their surrounding connections (to the die and to a leadframe, e.g.). One example is found in U.S. Pat. No. 4,821,148 (Kobayashi, et al., 4/89; USCL 361/392), entitled RESIN PACKAGED SEMICONDUCTOR DEVICE HAVING A PROTECTIVE LAYER MEAD OF A METAL-ORGANIC COMPOUND. In this patent, a silver electrode (4) on a leadframe (2) is bonded to an aluminum electrode (5) on a silicon chip (1). The resulting assembly is immersed in a solution of benzotriazole (BTA) in ethyl alcohol. An Ag-BTA film is formed on the surface of the silver electrode, an Al-BTA film is formed on the surface of the aluminum electrode, and a Cu-BTA film is formed on the surface of the copper wire. These three metal-BTA films protect the wire and the electrodes from damage by (environmental) dampness. Notably, in this patent, it is immaterial, at best, whether the metal-BTA films are conductive, interconnection (of die to leadframe) having previously (prior to coating) been achieved by the wire bond itself. Preferably, such a “hermetic” coating would not be conductive, as it would tend to short out the device (die).
Pins, i.e. elongated rigid electrically-conductive elements, are well known, and are generally brazed to pads on electronic packages (including chip carriers).
U.S. Pat. No. 3,373,481 (Lins, et al.; 3/68; USCL 29/471.3), entitled METHOD OF ELECTRICALLY INTERCONNECTING CONDUCTORS, discloses forming pin-like gold pedestal structures (13) atop terminal portions (12) of an integrated circuit device (10) by thermocompressing gold spheres (13, see FIG. 2) and shaping the spheres with a heated vacuum holder (14). The use of an ultrasonic bonder in lieu of the vacuum holder is discussed. As shown in FIG. 3 of the patent, a bond is formed between the pedestal structure (13) and what appears (in the side view) to be the entire surface of the terminal (12).
U.S. Pat. No. 4,418,857 (Ainslie, et al.; 12/83; USCL 228/124), entitled HIGH MELTING POINT PROCESS FOR AU:SN:80:20 BRAZING ALLOY FOR CHIP CARRIERS, discloses an exemplary technique for brazing pins to chip carrying substrates.
U.S. Pat. No. 4,914,814 (Behun, et al.; 4/90; USCL 29/843), entitled PROCESS OF FABRICATING A CIRCUIT PACKAGE, discloses filling an array of pin holes in a pin mold with lead/tin solder, which array of pin holes is in substantial registration with an array of conductive pads on one side of a chip carrier, heating the lead-tin solder in the pin mold such that the solder becomes molten and coalesces with the array of conductive pads on the chip carrier, thereby forming an array of miniature “pins” bonded to the array of conductive pads on the chip carrier. This permits the formation of elongated, solder terminals of controlled height and, apparently, of relatively high aspect ratio.
U.S. Pat. No. 4,955,523 (Carlomagno, et al.; 9/90; USCL 228/179), entitled INTERCONNECTION OF ELECTRONIC COMPONENTS, discloses a technique for interconnecting electronic components in which interconnection wires are bonded to contacts on a first component (such as a semiconductor die (1)) without the use of a material other than the materials of the contacts and the wires. The wires are then severed to a desired length of between two to twenty times the wire diameter (2d to 20d), and bonded to contacts on a second component (21) by means of a conductive material such as solder. The wires, once bonded to the first component, are severed at their desired length (by the bonding head (9) of a wirebonder) via an aperture (13) in the side wall of the bonding head. To this end, an electrode (51) is inserted into the aperture (13). As shown in this patent, the free-standing wires (7) have their ends inserted into pools (27) of conductive material such as solder in recesses of the second component. See also U.S. Pat. No. 5,189,507 (Carlomagno, et al.; 2/93; USCL 257/777), also entitled INTERCONNECTION OF ELECTRONIC COMPONENTS.
Surface mount technology solves certain problems associated with making interconnections between electronic components, but has proven itself not to be the panacea it was once envisioned to be. Generally, in surface mount technology (SMT), including flip-chip technology, solder bumps are formed on a face of a first electronic component, pads are provided on a face of a second electronic component, and the components are brought together, face-to-face, after which heat is applied to reflow the solder of the solder bumps. The challenges to effecting reliable surface mount include forming solder bumps with controlled geometry and high aspect ratio (ration of height to width), sometimes referred to as “solder columns”.
U.S. Pat. No. 5,130,779 (Agarwala, et al.; 7/92 USCL 357/67), entitled SOLDER MASS HAVING CONDUCTIVE ENCAPSULATING ARRANGEMENT, describes “elongated” solder columns having high aspect ratios. On an “electronic carrier” (substrate), a pad is formed on which a first solder mass is deposited and capped with a metal layer. An additional (second) solder mass is formed atop the first solder mass. An additional (third) solder mass may be formed atop the second solder mass.
Burn-in and testing is another field of endeavor which employs a plurality of temporary connections to be made between a first electronic component such as a semiconductor die and a second electronic component such as a test card. As discussed in greater detail hereinbelow, this typically involves first packaging the semiconductor die, and contacting pins on the package with special test fixtures such as a “bed of nails” (array of springy pins) arranged in a pattern corresponding to the pattern of pins on the semiconductor package. The manufacture of such test fixtures is a specialty requiring a different test fixture for each array pattern, and is consequently both expensive and time-consuming.
Making resilient interconnections between electronic components is generally known to be desirable, and has been the object of prolonged endeavor. Often (e.g., typically), external connections to semiconductors devices are relatively rigid pins disposed on an exterior surface of a package. Some effort has been made in the past to implement resilient interconnection structures. In some instances, resilient connections have been effected with metal elements. In other instances, resilient connections have been effected with a combination of metallic elements and elastomeric elements.
One recent effort directed to making resilient connections is described in an article entitled ELASTOMERIC CONNECTOR FOR MCM AND TEST APPLICATIONS, ICEMM Proceedings, 1993, pages 341–346, which describes an “Elasticon”™ connector. The Elasticon connector uses solid gold or gold alloy wires for the conductive elements, embedded in an elastomer material (e.g., liquid elastomer resin injected into a mold cavity), and is generally targeted at the interconnection requirements for land grid array (LGA) packages for multichip (MCM) and single (SCM) chip modules. The size, shape and spacing of the wires, along with the elastomer material properties, can be tailored to specific application requirements which include MCM and SCM packaging, board-to-board and cable-to-board interconnections, as well as high density PCB and IC chip testing applications. The solid gold wires and the silicone elastomer material are impervious to corrosion. FIG. 1 of the article illustrates a basic embodiment of the Elasticon connector, wherein a plurality of wires are ball-bonded to a rigid substrate and extend straight at an angle (e.g., 45–85°) from the surface of the substrate. Attachment of the proximal ends of the wires to the substrate is by an angled flying lead wire bonding process using compressive force and ultrasonic energy applied through the capillary tip and thermal energy applied through the heated stage on the wirebonder. The capillary and substrate are positioned to allow a shear blade mechanism to sever the wire at the desired height and angle from the substrate surface. Electronic flame-off (EFO) is used to melt the wire extending from the capillary tip to start the next ball bond (of the proximal end of the next wire to be bonded to the substrate). After mounting all of the wires to the substrate, a ball-shaped contact is formed at the far (distal) end of each wire by a process of laser ball forming, and the plurality of wires are embedded in an elastomer material. The ball-shaped (enlarged) distal ends help prevent the wires from vibrating loose and causing shorts between contacts. As noted in the article, the angled orientation of the conductors is necessary to minimize plastic deformation of the wires as an Elasticon connector is compressed between two parallel surfaces. The angled orientation also provides a “wiping” contact surface which, when the connector is compressed, will cause the wires to rotate and slide against the mating contact surfaces. The article discusses the use of gold/palladium alloys and platinum for the wires. FIG. 3 of the article describes clustering wires in groups of one to four wires per contact, in conjunction with forming grooves in the elastomer between each group of wires. The various embodiments of the Elasticon connector described in the article require a substrate of ceramic, metal, silicon or epoxy-glass laminate material, and interposer embodiments require an etchable substrate material such as copper with a thin layer of gold on the top surface. FIG. 8 of the article describes integrated probe contacts and aptly notes that the ability to test for known good dies has been one of the stumbling blocks for MCM packaging. As shown therein, a probe matrix uses 2 mil (0.002 inch) diameter gold wires in an array. The probes can permanently be attached to the test module, or fabricated as an interposer structure. U.S. Pat. No. 5,386,344 (Beaman, et al.; 1/95; USCL 361/785), entitled FLEX CIRCUIT CARD ELASTOMERIC CABLE CONNECTOR ASSEMBLY, discloses a related “Elastipac”™ elastomeric cable connector.
Another illustrative effort at making resilient connections may be found in U.S. Pat. No. 5,299,939 (Walker, et al.; 4/94; USCL 439/74), entitled SPRING ARRAY CONNECTOR, which discloses independently bendable springs with significant horizontal elasticity, including sine, helix, cantilever, and buckling beam shapes in sheet and wire forms. A connector formed thereby provides substantial compliance in order to provide compensation for variations, including manufacturing tolerances, alignment tolerances, and thermo-mechanical expansion. Fabrication of the spring connectors proceeds generally as follows. A three-dimensional mandrel defines the inner surface shape of the spring (12). An insulating layer (50) is applied on the spring (12). A conducting layer (14) is applied on the insulating layer at predetermined locations. A plurality of springs (12) are formed as a unitary sheet layer of resilient material (38), which can readily be deposited (on the mandrel), such as nickel 96%-phosphorous 4% and nickel 97%-cobalt 3%. The mandrel is removed after depositing the spring layer (38). Alternatively, the mandrel may be “sacrificial”, such as is known in the art of “lost wax” “casting”. Using a resilient wire as the spring layer (e.g., as an alternative to using a sheet) is discussed, and includes a wire (204), covered by an insulating layer (21), covered by a segmented conductive layer (212), covered by an outer insulating layer (214). The resulting spring connector is principally (if not solely) directed to making contact (versus attachment). As aptly set forth in the patent:
“a distinction must be made between two types of electrical connection: attachment and contact. Attachment is [a] relatively permanent connection and typically involves a durable metallic connection, such as solder, micro-brazing or micro-welding connection. Contact is a relatively temporary connection and implies a segmented connection between mating conductors, usually dependent upon a compressive force without the presence of a durable metallic connection.”
Another illustrative effort at making resilient connections may be found in U.S. Pat. No. 4,067,104 (Tracy; 1/78; USCL 29/626), entitled METHOD OF FABRICATING AN ARRAY OF FLEXIBLE METAL INTERCONNECTS FOR COUPLING MICROELECTRONIC COMPONENTS. This patent discloses fabricating an array of cylindrical columns, such as several layers of indium, on active devices, such as semiconductors, wherein the columns can flex to accommodate differential thermal expansion.
U.S. Pat. No. 4,793,814 (Zifcak, et al.; 12/88; USCL 439/66), entitled ELECTRICAL CIRCUIT BOARD INTERCONNECT, discloses a connector arrangement for providing electrical interconnection between corresponding contact pads of opposed first and second circuit boards and includes an electrically nonconductive support member which includes resilient elastomeric material. An electrically conductive interconnect element extends through the thickness of the support and has a pair of pad engagement surfaces disposed to engage the respective contact pads.
U.S. Pat. No. 4,330,165 (Sado; 5/82; USCL 339/59), entitled PRESS-CONTACT TYPE INTERCONNECTIONS, discloses an interconnector composed of an elongated rod member (1) made of a rubbery elastomer, a plurality of linear electrically conductive bodies (2) embedded in the rod member (1), and two sheet members (3,3) bonded to the lateral surfaces of the rod member (1). The ends of the linear bodies (2) appear on the opposite surfaces, i.e. the top surface and the bottom surface, of the rod member (1), forming the contacting surfaces with the circuit boards between which the interconnector is to be mounted as sandwiched. The linear conductive bodies (2) are each a ribbon of, for example, a metal.
U.S. Pat. No. 4,295,700 (Sado; 10/81, USCL 339/61), entitled INTERCONNECTORS, discloses a press-type interconnector having rectangular connecting piece made of a sheet or film of elastic material, which is an assembly of alternating electroconductive elastic material and electrically-insulating material so that the rectangular piece, as a whole, has a plurality of electrically conductive paths (i.e., the electroconductive stripes). The rectangular connecting piece is sandwiched between two holding members which are made of an insulating material.
U.S. Pat. No. 3,795,037 (Luttmer; 5/74; USCL 29/628) entitled ELECTRICAL CONNECTOR DEVICES, discloses a plurality of bent or curved elongated flexible conductors embedded in, and extending between surfaces of a block of elastomeric insulating material. Exemplary flexible conductors are formed from any suitable electrically conductive resilient material such as, for example, phosphor bronze, and have exemplary cross-sectional dimensions on the order of 25 microns (μm), and may have a free length of 2 mm (millimeters).
U.S. Pat. No. 5,067,007 (Kanji, et al.; 11/91; USCL 357/54), entitled SEMICONDUCTOR DEVICE HAVING LEADS FOR MOUNTING TO A SURFACE OF A PRINTED CIRCUIT BOARD, discloses improving the reliability of surface-mount type packages so that when the packages are mounted to a wiring substrate the lead pins that receive load from the axial direction exhibit bending strength which is smaller than the junction strength at the junction portions. To achieve this object, the lead pins are made of a material having large resiliency such as fiber-reinforced material, a transformation pseudo elastic material, an ultra-high tension material, or a heat-resistant ultra-high tension material. This patent also points out the problem that, in the case of pin grid array (PGA) packages, all of the pins are not necessarily of the same length—the result of which is that some of the pins may not contact pads (e.g., on a test substrate). FIGS. 7A and 7B of this patent are of particular interest, wherein pins (20) have a particular shape and are formed of a particular material. The pins (20 are made of a material having Young's modulus of smaller than 15×1010 Pa, and have their central portions curved in an arcuate form such that the displacement from the axial (straight) direction becomes greater than one half the diameter of the pins. Examples of materials satisfying the Young's modulus criteria are: highly pure copper (Cu), highly pure iron (Fe), highly pure nickel (Ni), copper alloy, and a composite wire comprising of a stringly (sic) resilient fine wire bundled with a soft metal such as copper as a binding material. With such a shape, and being formed of such materials, the deformation strength (yield strength) of the pins becomes smaller than the junction strength of either the brazing material (12, holding the pin to the package) or the solder (13, connecting the pin to the PCB). When thermal or mechanical stresses are exerted on the pins, they undergo elastic deformation to reduce the stress. In an exemplary embodiment shown in FIG. 1D and described with respect thereto, tungsten (W) molybdenum, carbon amorphous metal and fine wires having large resiliency are described. The fine wire may be a composite wire (11A) which is bundled together with a soft metal such as copper as the binding material. The composite wire has a plating (11B) which comprises gold (Au) or gold/nickel. Gold, as discussed hereinabove, is very soft, and inherently not resilient. As specifically mentioned in this patent, “the thickness of the plating is so small that the effect to the bending strength [of the composite wire 11A] can be neglected. The plating is effected for the purpose of easy soldering and, concretely (sic), has a thickness of 1 to 4 μm for nickel and 0.1 to 1 μm for gold.” (see paragraph bridging columns 7–8).
U.S. Pat. No. 5,366,380 (Reymond; 11/94; USCL 439/66), entitled SPRING BIASED TAPERED CONTACT ELEMENTS FOR ELECTRICAL CONNECTORS AND INTEGRATED CIRCUIT PACKAGES, discloses a contact element for an electrical connector of for an integrated circuit package (ICP), which is particularly useful for surface mount applications. The contact element has a base portion, a spring portion having at least partially helical spring elements, and a tapered contact portion which mates in a biased manner with a conductive rim of a hole, and can be fabricated from a flat sheet with punching, rolling, and/or forming operations, thin-walled drawn parts, or modular parts. The contact elements are maintained in a compressed state by a hold-down mechanism. The contact elements can be associated with insulating housings and/or spacers which provide functions such as alignment, compression limitation, contact support, and installation fixturing.
U.S. Pat. No. 4,764,848 (Simpson; 8/88; USCL 361/408), entitled SURFACE MOUNTED ARRAY STRAIN RELIEF DEVICE, discloses mounting “roots” of relatively-thin pin-like electrical conductors (22) extending through pin holes in a substrate (16) to which an integrated circuit chip or similar electronic component or device (18) is mounted. The pins (22) are fabricated of an electrically conductive material such as copper, and each pin has at least two bends between its root and its tip for providing strain relief when the tip of the pin is connected to a surface.
U.S. Pat. No. 5,317,479 (Pai, et al.; 5/94; USCL 361/773), entitled PLATED COMPLIANT LEAD, discloses a curved lead which provides a mechanical and electrical connection between a board contact on a circuit board and a chip contact associated with a circuit chip. The curved lead is substantially entirely plated with solder, and is formed of a single piece of conductive material. Generally, the curved lead has two parallel surfaces, one for connecting with the chip contact and one for connecting with the board contact, and at least one curved portion therebetween. The leads are preferably formed from a thin strip of material and, for example, may be 0.018 inches wide and 0.070 inches in overall (e.g., prior to bending) length, and are preferably formed of thick copper beryllium and cobalt alloy 0.003–0.005 inches thick. The lead is covered with solder in a manner which is carefully controlled so that excess solder does not interfere with the desired compliance of the lead.
U.S. Pat. No. 4,989,069 (Hawkins; 1/91; USCL 357/74), entitled SEMICONDUCTOR PACKAGE HAVING LEADS THAT BREAK-AWAY FROM SUPPORTS, discloses a stress buffer frame (16) having flexible metal leads (26) reducing stress caused by the differing coefficients of thermal expansion of a semiconductor package and a printed circuit or the like on which the package is mounted. The leads are essentially flat ribbon-like leads, which are bent to extend away from the buffer frame, then bent again to have a portion (32) parallel to the buffer frame. Nickel/iron alloy is discussed as a material for the frame (and leads thereof).
One reason to provide a degree of compliance in electrical connections is to absorb stresses which occur due to thermal cycling. Generally, as a semiconductor device (die) operates, it generates heat. This causes the die to expand, often at a different rate than the package in which the die is mounted and, similarly, at a different rate than the electrical connections between the package and the die. (Assuming that the heat generated by the die is fairly uniform throughout the die, the die will tend to expand about its centroid, or center of symmetry.) This is similarly the case with surface mounted dies, with the die expanding at a different rate than the board to which it is mounted (and the electrical connections between the die and the board). The difference in thermal coefficients of expansion between the die and surrounding elements (e.g., package, board, electrical connections) results in mechanical stress. Generally, it is desired to account for, and to reduce, such thermally-induced mechanical stresses. For example, U.S. Pat. No. 4,777,564 (Derfiny, et al.; 10/88; USCL 361/405); entitled LEADFORM FOR USE WITH SURFACE MOUNTED COMPONENTS, discloses an electrical connection extending from an electronic component and connecting to a printed circuit board which is highly resistant to stress-related failures resulting from thermal cycling.
U.S. Pat. No. 5,086,337 (Noro, et al., 2/92; USCL 357/79), entitled CONNECTING STRUCTURE OF ELECTRONIC PART AND ELECTRONIC DEVICE USING THE STRUCTURE, discusses the desirability of having deformability (freedom) and “flexibility” (spring property) in a perpendicular (z) direction at the junctions between LSI chips (semiconductor dies having Large Scale Integration) and a wiring substrate. (see, e.g., column 4, lines 50–55). This patent discloses a connecting structure for electrically connecting an electronic part, such as an LSI chip, to a substrate, such as a wiring substrate, having an absorption function of the difference of thermal expansion in a horizontal direction (e.g., in the plane of the chip) and capability of displacement in a vertical (z-axis) direction. A representative embodiment of the connecting structure is shown in FIGS. 2(a), 2(b) and 2(c), wherein the connecting structure is in the form of a flat, spiral spring, a one end of the flat spiral spring being connected to a one electronic component, and another end of the flat spiral spring is connected to another electronic component. This allows for displacement of the two components in the z-axis, while maintaining a connection therebetween. The flat, spiral spring connectors are generally formed as a Cr—Cu—Cr “sandwich”, which is annealed and coated with Au to improve its solder-wettability (Cr being comparatively non-wettable as compared with Au). See also U.S. Pat. No. 4,893,172 (Matsumoto, et al.; 1/90; USCL 357/79), entitled CONNECTING STRUCTURE FOR ELECTRONIC PART AND METHOD OF MANUFACTURING THE SAME. (It should be noted that, in the present patent application, the term “flexibility” is generally associated with plasticity, and that the term “resiliency” is generally associated with springiness.)
As a general proposition, it is much easier to fabricate a resilient contact structure on electronic components other than semiconductor dies, due to the fragility (delicate nature) of semiconductor dies. This has led to the development of “passive” electronic components which have resilient contact structures incorporated therein and which, in use, are disposed (i.e., interposed) between two electronic components having corresponding contact pads.
U.S. Pat. No. 4,642,889 (Grabbe; 2/87; USCL 29/840), entitled COMPLIANT INTERCONNECTION AND METHOD THEREFOR, discloses placing an interposer having interconnect areas between a circuit board and a device to be surface mounted with interconnect areas disposed between conductive strips on the circuit board and pads contained on the surface mount device. The interconnect area of the interposer has disposed therein a plurality of fine wires having flux and solder. The desirability of having a high solder pedestal so that substantial compliance will be available to compensate for thermal coefficient of expansion mismatch (“potato-chipping”) is disclosed, as well as the desirability of implementing such high solder pedestals in an interposer.
U.S. Pat. No. 3,509,270 (Dube, et al.; 4/70; USCL 29/625), entitled INTERCONNECTION FOR PRINTED CIRCUITS AND METHOD OF MAKING SAME, discloses an insulating body (2) having an aperture (4) extending therethrough with a compression spring (6) inserted therein. The insulating body, with springs inserted into its apertures and extending out of the apertures, is sandwiched between two electrically conducting circuit members (8, 10), which are bonded to the insulating body with resin layers (12). The springs are disclosed as being made of gold alloy containing platinum, silver, copper and zinc, and may be provided with a coating of solder.
U.S. Pat. No. 3,616,532 (Beck; 11/71; USCL 174/68.5), entitled MULTILAYER PRINTED CIRCUIT ELECTRICAL INTERCONNECTION DEVICE, discloses a similar (to Dube, et al.) interconnection arrangement, wherein coil springs are compressed and inserted into a pot of molten solder, and subsequently withdrawn from the pot and the solder allowed to solidify to thereby hold the coils of the compression spring tightly together against the restoring force of the spring. These compressed springs are then inserted into apertures of an interposer-layer 24 which is disposed between two printed circuit boards (10, 12). The assembly (board, interposer with precompressed springs, board) is the heated such that the solder holding the coils of the springs again liquifies and releases the spring tension. The springs are therefore permitted to expand and to establish contact between the abutting printed circuit levels (boards).
U.S. Pat. No. 4,667,219 (Lee, et al.; 5/87; USCL 357/68), entitled SEMICONDUCTOR CHIP INTERFACE, discloses a connector plate (80) having a plurality of apertures (82) disposed beneath a semiconductor chip (18) having an array of contacts (44,46,48). The apertures of the plate are aligned with the contacts of the chip. A plurality of flexible conductors (described as S-shaped copper wires 84 in FIG. 8) extend through the respective apertures of the connector plate to connect (e.g., be soldered) to the chip contacts and terminals (transmission elements 64,67,72) disposed below the connector plate. Thus, each contact on the chip is flexibly and electrically coupled to a respective one of the terminals.
U.S. Pat. No. 4,705,205 (Allen, et al.; 11/87; USCL 228/180), entitled CHIP CARRIER MOUNTING DEVICE describes an “interconnection preform placement device” (also known as an “interposer”). In FIGS. 11A–11C, 12 and 13 of the patent there are described a variety of solder “preforms” which have S-shapes (FIGS. 11A, 11B, 11C) or C-shapes (FIG. 12), or a coiled spring configuration (FIG. 13). The preforms are disposed in apertures (holes) through support (“holder”, “retaining”) layers (e.g., 50 and 52 in FIG. 11A). The C-shaped preform is disposed around the edge of a support layer. The preforms are a “filled solder composition” (a solder material which contains a filler of discrete particles or filaments) or a “supported solder” (solder supported by a support strand or tape which is disposed about the outside of the solder preform shape), which will retain its shape upon the solder melting or reflowing. For example, the particles in a filled solder composition should have a melting point above the melting point of the solder. Filler materials such as copper, nickel, iron, and metal-coated high-temperature polymer or glass films are disclosed and, as mentioned, can be in the form of discrete particles (e.g., powders) or continuous lengths with a single strand or many strands in each preform.
As mentioned hereinabove, electronic components are often connected to printed circuit boards (PCBs), also known as printed wiring boards (PWBs). Printed circuit board (PCB) technology is well developed, and generally involves forming conductive traces on an insulating substrate to effect often complex interconnections between electronic components mounted to or plugged into the PCB. PCBs having conductive traces on both sides of the board are known, as well as multi-layer arrangements of alternating insulating and conductive layers. Additionally, effecting connections from layer-to-layer, within the PCB, are generally well known. A more comprehensive discussion of basic PCB technology can be found in Printed Circuits in Space Technology, Linden, Prentice-Hall Inc., 1962, incorporated by reference herein. It should clearly be understood that, in any of the embodiments described hereinbelow setting forth PCB substrates, these substrates can be formed of materials other than “traditional” printed circuit board materials. For example, the “PCB” substrate can be formed of one or more layers of plastic material, such as polyimide, optionally with conductive foil layers sandwiched therebetween, as is known. The term “circuitized” will also appear hereinbelow, and refers to the conductive patterns, and the like, present on PCB substrates.
U.S. Pat. No.4,532,152 (Elarde; 7/85; USCL 427/96), entitled FABRICATION OF A PRINTED CIRCUIT BOARD WITH METAL-FILED CHANNELS, discloses a plastic substrate which is injection molded to provide a pattern of channels in at least on of its sides to define a predetermined set of conductive paths. Metallizing the substrate by flame spraying, electroless plating, electroplating, gas plating or vacuum deposition is disclosed. The substrate (e.g., 20 in FIG. 12) may be provided with plated through holes (58) permitting electronic components mounted on one side of the printed circuit board to be electrically interconnected to conductive paths on the other side of the printed circuit board. This patent is cited simply as being illustrative of plated through holes.
Generally, each of the aforementioned techniques for effecting electrical connections between electronic components requires its own “methodology”—in other words, each requires its own distinct type (e.g., bond wires, pins, etc.) of connection structure.
Moreover, each of the aforementioned techniques suffers from inherent limitations. For example, replacing a first electronic component that is permanently connected to a second electronic component typically requires carefully un-soldering the first electronic component from the second electronic component, then carefully soldering a replacement first electronic component to the second electronic component. Sockets address this concern, but add (often unacceptable) cost to the overall system. Moreover, socketing tends to exhibit inferior connection reliability, as contrasted with soldered connections. Surface mount techniques, such as the aforementioned technique of providing the first electronic component with solder balls and providing the second electronic component with conductive pads require carefully controlled processes to effect reliably, and do not lend themselves well to disassembly (replacement of one of the electronic components).
Returning to the popularity of using gold to make connections between electronic components, although gold exhibits excellent electrical conductivity, it suffers from certain shortcomings, as relevant to the present invention. For example, gold has a very low yield strength, a characteristic which makes it extremely counter-intuitive to employ a gold wire in (or as) a resilient contact structure. Simply stated, when physically stressed, gold (e.g., a gold wire) will tend to deform, and to retain its deformed configuration. This is called “plastic deformation”.
Another shortcoming of using gold wires as an interconnect medium is gold's propensity to react with solder—namely with the tin content of common lead-tin solder. Notwithstanding this fact, certain “eutectic” materials are known, such as gold-tin, which tend to exhibit desireable interconnection properties. Eutectic materials and their properties are discussed in greater detail hereinbelow.